(Hong Kong)
Product Summary
The MT48LC2M32B2TG-5 is a high-speed CMOS, dynamic random-access memory containing 67,108,864-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the MT48LC2M32B2TG-5 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits.
Parametrics
MT48LC2M32B2TG-5 absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3)Operating Temperature, TA: 0℃ to +70℃; (4)Extended Temperature: -40℃ to +85℃; (5)Storage Temperature (plastic): -55℃ to +150℃; (6)Power Dissipation: 1W.
Features
MT48LC2M32B2TG-5 features: (1)PC100 functionality; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7)Self Refresh Mode; (8)64ms, 4,096-cycle refresh (15.6μs/row); (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ?.3V power supply; (11)Supports CAS latency of 1, 2, and 3.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
|---|---|---|---|---|---|---|---|---|---|---|
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 MT48LC2M32B2TG-5:G |
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IC SDRAM 64MBIT 200MHZ 86TSOP |
Data Sheet |
Negotiable |
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MT48LC2M32B2TG-55:G |
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IC SDRAM 64MBIT 5.5NS 86TSOP |
Data Sheet |
Negotiable |
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MT48LC2M32B2TG-55:G TR |
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IC SDRAM 64MBIT 5.5NS 86TSOP |
Data Sheet |
Negotiable |
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